Verilog: use time delay in for loop -


i creating multiple calls module module using generate in loop. need make calls module after few delay rather instantly. unable add using #<time delay>. throwing compilation error like:

error: c:\altera\13.0\test.v(53): near "#": syntax error, unexpected '#'

could please me out? below code snippet:

generate   genvar i;    (i=0; i<12; i=i+1) begin      #10 custom i_custom(clock, reset, in , out);   end endgenerate


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